SLAAC-1
SLAAC-1 is an attached FPGA-based accelerator on a full-sized 64-bit PCI board. SLAAC-1 features one user-programmable Xilinx 4085 device, two user-programmable Xilinx 40150 devices, and ten 256Kx18 100MHz ZBT synchronous SRAMs.
Status
| 5/11/00 | Wow, haven't been to this page in a
while... The SLAAC-1 series has been in wide use within the team
since about September 1999. It has all of the basic
functionality necessary to make it a true reconfigurable computing
board, including:
There are two revision levels of SLAAC-1 hardware. Rev A has a number of wire mods, but is functional. Rev B added two LEDs to the X0 part and moved readback control over to the Xilinx mode (MD0 and MD1) pins. The main reason we did this was to incorporate a number of net changes with the interface FPGA. |
| 5/20/99 | Peter is making great progress with the Xilinx PCI Dev Kit core and driver kit. The device driver is able to recognize the PCI core Ping demo on SLAAC-1. Next task is to port the PowerPC bus debugger and start inserting interface modules from the SLAAC-2 core. |
| 4/30/99 | SLAAC-1 IF device blinking lights with simple Xchecker downloaded design. We should be ready to plug board into PCI bus. Work on the PCI core has started. |
| 4/26/99 | Short resolved! Not as bad as we feared, can be fixed with a simple mod. |
| 4/21/99 | SLAAC-1 has an unresolved short in 3.3V which does not appear until after assembly of the front side. Possibly a solder bridge under one of the BGAs. May be a manufacturing problem warping the board. Hardware team working on it with vendors. Not in critical path yet, as the rest of the team is consumed with SLAAC-2. We purchased a Xilinx PCI development kit with board to allow PCI interface development to continue while this is resolved. |
| 4/2/99 | A fit test with the QC64 I/O board from Los Alamos National Lab was successful. |
| 4/1/99 | A fully-populated SLAAC-1 PCI board arrived at ISI. Power testing has begun. |
Photos
Here are some photos of various SLAAC-1 components. Click on an image to open a full-page view.
SLAAC-1 Front
SLAAC-1 Back
SLAAC1 Memory Module
LANL QC65 I/O Board
Architecture
SLAAC-1 has two user-programmable processing elements and one user-programmable control element.
Processing Element
The SLAAC-1 processing element has one Xilinx 40150 FPGA and four 256Kx18 synchronous SRAMs. There are three primary 72-bit data paths into the FPGA, a left and right path to adjacent FPGAs on the systolic ring and a shared crossbar bus.
