SLAAC-2
SLAAC-2 is an attached FPGA-based accelerator on a 6U VME mezzanine board. SLAAC-2 features two user-programmable Xilinx 4085 devices, four user-programmable Xilinx 40150 devices, and twenty 256Kx18 100MHz ZBT synchronous SRAMs.
Status
| 5/20/99 | A final "alpha" version of the interface logic is nearly completed. Simple slave read/write FIFOs have been tested and are working fine. We wrote a simple design that circumnavigated all of the user FPGAs and latched values on the LEDs. Writing to the EEPROM is the next step so we can remove the necessity of the download cable. Matt is cleaning up this version to pass along to Peter to port the interface modules to SLAAC-1. |
| 5/3/99 | Testing of the thermo-monitor completed. PowerPC core appears limited to 64-bit transactions, so for now we are going to align IF memories on 8-byte boundary and introduce bank select register. |
| 4/21/99 | SLAAC-2 testing progressing and going well. We were able to verify clock synthesizer programming. Fixed a bug in driver code that caused clock to fail reprogramming once programmed. Memory test successful (sort of). Need to add byte-swap logic to write to odd 32-bit data words. Hey, we can read and write to half the words in the IF memories :-). |
| 4/15/99 | SLAAC-2 testing continues. We're able to configure the user FPGAs and verified program the clock synthesizer. Access to the IF memories is being tested now. Testing of the IF FIFOs is scheduled for next week. |
| 4/7/99 | First successful PowerPC core transaction! We're able read and write to registers inside the IF device. |
| 4/1/99 | A fully-populated SLAAC-2 PCI board arrived at ISI. Power testing has begun. |
Photos
SLAAC2 Front
SLAAC2 Back
Architecture
SLAAC-2 is actually two “independent” SLAAC-1 bit-file compatible accelerators on a single board. This mezzanine plugs into a modified CSPI 2641 quad PowerPC baseboard, the M2641S.