Architecture

 

Background

The goals of the SLAAC effort are to: 1) create a design methodology, open architecture definition, and runtime environment based on emerging EHPC and ACS component technology; 2) create a generic reference implementation for the research community to accelerate technology demonstration and insertion across several signal processing domains; and 3) validate the reference implementation in the SAR/ATR domain to demonstrate 500x improvement in performance density.

The SLAAC architecture is based upon a high-speed network of ACS-accelerated nodes.   We believe that this architectural approach will enable us to accomplish all of the goals stated above.


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Research Reference Platform

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The SLAAC Research Reference Platform (RRP) is defined as a high-speed network cluster of traditional desktop PCs where each is accelerated with some form of ACS accelerator (such as a PCI FPGA-board).  The RRP has the advantage of being an inexpensive readily available platform for ACS development that tracks advances in workstations, adaptive computing, and cluster computing.

The Tower of Power (ToP) at Virginia Tech is a good example of an existing RRP. The ToP has sixteen Pentium II PCs each equipped with a WildForce board tightly coupled to a Myricom LAN/SAN card; the PCs are connected through a sixteen port Myrinet switch. A total of 80 XC4062XL FPGAs and memory banks are distributed throughout the platform, and are available as computing resources.

gothere.gif (982 bytes) Virginia Tech Tower of Power home page.

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Deployable Reference Platform

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Migration of applications that are developed in the lab environment on the RRP system to deployed systems requires cluster-computing  to exist in field-friendly environments such as VME.  Fortunately, commercial systems have evolved from the DARPA Embedded High-Performance Computing (EHPC) program that address this need. 

An example of this is the CSPI 2641 MultiComputer, a high-performance digital signal processor module, combines Myrinet gigabit network technology with the PowerPC architecture to deliver an open and expandable solution for high-performance computing applications. Packaged in an industry standard 6U VME form factor, the 2641 MultiComputer delivers 2.4 GFLOPS of peak computational power.

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The task remaining to SLAAC  is to introduce ACS accelerators into these EHPC systems.  The scalable API and runtime control software being developed for the RRP are also under development in a VxWorks environment for Single Board Computers (SBCs). This field-friendly version of the RRP is referred to as the Deployable Reference Platform (DRP).

gothere.gif (982 bytes) CSPI home page.

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